vishay siliconix SIP1759 document number: 72949 s09-1453-rev. d, 03-aug-09 www.vishay.com 1 buck-boost regulator description the SIP1759 is a buck-boost regulating charge pump. it is designed to provide a regulated output from 1 cell li ion or 2/ 3 cell nimh voltages found in handheld portable equipment, 1.6 v to 5.5 v. SIP1759 allows the option of a fixed 3.3 v output voltage, or an adjustable output which can be set from 2.5 v to 5.5 v. the output current is up to 100 ma. for flexibility in application, SIP1759 has a shutdown pin (sd ) and an error output to indicate when the output voltage is in regulation. SIP1759 is available in a 10 pin msop package and is rated over the industrial temperature range of - 40 c to 85 c. features ? output voltage - fixed 3.3 v or adjustable from 2.5 v to 5.5 v ? 1.6 v to 5.5 v input voltage range ? 100 ma output current ? 60 a quiescent current ? shutdown current < 1 a ? short circuit crotection ? thermal shutdown ? msop-10 package applications ? 1 cell li ion battery powered equipment ? 2 to 3 cell nimh battery powered equipment ? 2 to 3 cell alkaline battery powered equipment ? backup battery boost converters typical application circuit SIP1759 adjustable output voltage r c out fb pgnd gnd c x+ c x- v out c in c x fixed output SIP1759 r c out fb pgnd gnd c x+ c x- pgnd c in c x r 1 error v in sd v in sd v out error r 2
www.vishay.com 2 document number: 72949 s09-1453-rev. d, 03-aug-09 vishay siliconix SIP1759 notes: a. device mounted with all leads soldered or welded to pc board. b. derate 5.6 mw/c above 25 c. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings (all voltages referenced to gnd = 0 v) parameter limit unit input voltage (v in ) - 0.3 to 6 v out sd , fb, error to gnd - 0.3 to 6 c x- to gnd - 0.3 to (v in + 0.3) c x+ to gnd - 0.3 to (the greater of v in or v out ) + 1) storage temperature - 55 to 150 c maximum junction temperature 150 power dissipation a,b msop-10 (t a = 70 c) 444 mw recommended operating range (all voltages referenced to gnd = 0 v) parameter limit unit input voltage range 1.6 to 5.5 v output voltage adjustment range 2.5 to 5.5 c in 10 f c x 0.33 c out 10 operating temperature range - 40 to 85 c specifications parameter symbol test condition unless specified v in = v sd = 2 v, fb = pgnd = gnd c in = 10 f, c x = 0.33 f, c out = 10 f temp. a limits - 40 c to 85 c unit min. typ. b max. input voltage range v in full 1.6 5.5 v input undervoltage lockout v uvlo full 0.7 1.0 1.5 output voltage adjustment range 1.6 v v in 5.5 v full 2.5 5.5 output voltage v out 2 v v in 5.5 v, 1 ma i out 50 ma 0 c to 85 c 3.17 3.3 3.43 2.5 v v in 5.5 v, 1 ma i out 100 ma 3.17 3.3 3.43 2 v v in 5.5 v, 1 ma i out 50 ma full 3.15 3.45 2.5 v v in 5.5 v, 1 ma i out 100 ma 3.15 3.45 maximum output current i out(max) 2.5 v v in 5.5 v full 100 ma transient load current i out 100 ma (rms) 0 c to 85 c 200 quiescent supply current i q v in = v sd = 4 v, v fb = 0 v, stepping down full 60 100 a v in = v sd = 2 v, v fb = 0 v, stepping up 60 100 shutdown supply current i qsd 1.6 v v in 5.5 v, v sd = 0 v full 1 5 output leakage current in shutdown sd v in = 2 v, v out = 3.3 v, v sd = 0 v full 1 5 sd logic input voltage v il 1 6 v v in 5 5 v full 0.25 * v in v v ih full 0.7 * v in sd input leakage current v sd = 5.5 v full - 1 1 a fb regulation voltage v fb v in = 1.65 v, v out = 3.3 v full 1.205 1.235 1.265 v fb input current i ifb v fb = 1.27 v full 25 200 na
document number: 72949 s09-1453-rev. d, 03-aug-09 www.vishay.com 3 vishay siliconix SIP1759 notes: a. full = as determined by the operating suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. pin configuration and truth table specifications parameter symbol test condition unless specified v in = v sd = 2 v, fb = pgnd = gnd c in = 10 f, c x = 0.33 f, c out = 10 f temp. a limits - 40 c to 85 c unit min. typ. b max. fb dual mode threshold internal feedback full 100 50 mv external feedback full 200 100 error trip voltage falling edge at fb full 1.0 1.1 1.2 v error output low voltage v ol i ol = 0.5 ma, v in = 2 v full 5 100 mv error leakage current v error = 5.5 v, v fb = 1.27 v full 0.01 0.2 a switching frequency f osc 1.6 v v in 5.5 v, v fb = 1 v full 1.2 1.5 1.8 mhz output short-circuit current v out = 0 v, 2.5 v v in 5.5 v foldback current limit full 110 ma thermal shutdown temperature temperature rising full 160 c thermal shutdown hysteresis full 20 efficiency v in = 3.6 v, i out = 10 ma full 90 % 10 error fb v in c x+ msop-10 sd v out 1 2 3 9 8 gnd pgnd top view 56 v in c x- 47 ordering information part number temperature range marking SIP1759dh-t1 - 40 c to 85 c 1759 eval kit temperature range board SIP1759db - 40 c to 85 c surface mount pin description pin number name function 1error open drain error flag - a low output indicate s that the output voltage is out of range 2sd shutdown input 3, 4 v in input voltage 5 gnd ground 6 pgnd power ground 7 c x- negative terminal of the charge pump capacitor 8 c x+ positive terminal of the charge pump capacitor 9 v out regulated output voltage 10 fb feedback input - connected to gnd for fixed 3.3 v output. connected to a resistive divider for an adjustable output
www.vishay.com 4 document number: 72949 s09-1453-rev. d, 03-aug-09 vishay siliconix SIP1759 functional block diagram detailed description the SIP1759 is a buck-boost regulating charge pump. this allows for the v in to be a higher or lower voltage than the regulated output. this is done with a charge pump that when v in is lower than v out is a regulated voltage doubler. when v in is higher than v out the charge pump is a step down gated switch. in boost mode, the ic controls the transfer capacitor through c x+ and c x- pins, switching the charge to the output keeping it regulated. in this mode the charge pump only switches to maintain regulation, the output ripple does not increase with light loads. in buck mode, the c x- pin is internally connected to pgnd and the c x+ is switched internally between v in and v out . unless v in is significantly larger than v out (v in v out + 1 v), in heavy load the is will slip from buck mode to boost mode as necessary to charge the transfer capacitor. shutdown mode the ic is designed to conserve power by decreasing current consumption during normal oper ation as well as shutdown mode. pulling the sd pin logic low, the output is disconnected from the input and is in high impedance; the internal circuitry of the osc illator, control logic, and the charge-pump switches are turned off, decreasing the current consumption to less than 1 a. undervoltage lockout when v in falls below 1 v the undervoltage lockout disables the SIP1759. power ok output pok is an open-drain output that goes low when the regulator feedback voltage falls below 1.1 v. a 10 k to 1 m pull-up resistor from pok to out should be used to provide a logic output and keep current consumption to a minimum. connect pok to gnd or leave floating if not used. the pok output is high impedance when the ic is in shutdown mode. fixed output the SIP1759 can be configured as a fixed 3.3 v output regulator or as an adjustable output from 2.5 v to 5.5 v. in the fixed 3.3 v output mode the feedback voltage is generated from the internal re sistor-divider network. the fb pin must be tied to gnd. soft-start and short circuit protection the ic features a soft-start me chanism that limits the inrush current during start-up and if the output is short circuited the SIP1759 limits the output current to 110 ma. thermal shutdown the sip 1759 is designed with a thermal shutdown circuit that will shut down the ic when the die temperature exceeds 160 c. the thermal shutdown has 20 c of hysteresis, insuring when the die cools down the ic will turn on again. - + - + oscillator control bias - + - + - + - + v in pgnd sd error gnd v out fb c x+ c x - s1 s2 1.235 v
document number: 72949 s09-1453-rev. d, 03-aug-09 www.vishay.com 5 vishay siliconix SIP1759 designs considerations setting the adjustable output voltage the SIP1759 regulated output c an be adjusted from 2.5 v to 5.5 v via resistor divider network from v out to gnd (see typical application circuits). r1 and r2 should be kept in the 50 k to 100 k range for low power consumption, while maintaining adequate noise immunity. the value r1 is calculated using the following formula: r1 = r2 {(v out /v fb ) - 1} v fb is nominally 1.235 v. capacitor selection capacitor selection for c in , c out and c x will have an impact in the voltage output ripple, output current and overall physical size of the circuit. ceramic capacitors are re commenced for their low esr ( 20 m ) which will help keep the output voltage ripple at a minimum. the initial values for the c in and c out capacitors should be 10 f, the c x capacitor should be 0.33 f. output voltage ripple the SIP1759 automatically decides whether to be in step up mode or step down mode depending on the v in , v out and current load conditions, ther efore the voltage output ripple will vary. in step-up mode the voltage output ripple is higher than step-down mode. but unless v in is significant larger than v out (v in v out + 1 v) , in heavy load the ic will slip from buck mode to boost mode as necessary to charge the transfer capacitor and the ripple will increase. reducing the c x capacitor value will cause an increase in the switching frequency and a reduction of the output ripple. typical characteristics efficiency vs. input voltage start-up input voltage 0 20 40 60 80 100 120 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) i out at 10 ma ) % ( y c n e i c i f f e i out at 50 ma i out at 100 ma 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) ) v ( e g a t l o v t u p t u o (v out < v in ) r load = 33 quiescent current vs. input voltage (no load) output voltage ripple vs. input voltage 1.00e-07 1.00e-01 input voltage (v) 0.5 1.5 2.5 3.5 5.5 4.5 ) a ( t n e r r u c t n e c s e i u q 1.00e-02 1.00e-03 1.00e-04 1.00e-05 1.00e-06 0.00 0.04 0.08 0.12 0.16 0.20 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) ) v ( e g a t l o v e l p p i r t u p t u o 10 ma 50 ma 100 ma
www.vishay.com 6 document number: 72949 s09-1453-rev. d, 03-aug-09 vishay siliconix SIP1759 typical waveforms vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72949 . figure 1. typical switching waveform (v out > v in ) figure 3. load transient response (v out > v in ) figure 5. turn on/off response (v in = 2.5 v) 5 s/div v in = 2.5 v v out = 3.3 v r load = 33 v out 50 mv/div v c+ 5 v/div v in 50 mv/div 100 s/div v in = 2.5 v v out = 3.3 v iout step: 10 ma - 100 ma v out 50 mv/div i out 100 ma/div i out 100 ma/div 0.5 ms/div v in = 2.5 v v out = 3.3 v v out 1 v/div i in 200 ma /div v error 5 v /div v sd 2 v/div figure 2. typical switching waveforms (v out > v in ) figure 4. load transient response (v out < v in ) figure 6. turn on/off response (v in = 4.2 v) 5 s/div v in = 4.2 v v out = 3.3 v r load = 33 v out 50 mv/div v c+ 5 v/div v in 50 mv/div 100 s/div v in = 4.2 v v out = 3.3 v iout step: 10 ma - 100 ma v out 50 mv/div i out 100 ma/div 0.5 ms/div v in = 4.2 v v out = 3.3 v v out 1 v/div i in 200 ma /div v sd 2 v/div v error 5 v /div
notes: 1. die thickness allowable is 0.203 0.0127. 2. dimensioning and tolerances per ansi.y14.5m-1994. 3. dimensions ?d? and ?e 1 ? do not include mold flash or protrusions, and are measured at datum plane -h- , mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimension is the length of terminal for soldering to a substrate. 5. terminal positions are shown for reference only. 6. formed leads shall be planar with respect to one another within 0.10 mm at seating plane. 7. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the lead foot. minimum space between protrusions and an adjacent lead to be 0.14 mm. see detail ?b? and section ?c-c?. 8. section ?c-c? to be determined at 0.10 mm to 0.25 mm from the lead tip. 9. controlling dimension: millimeters. 10. this part is compliant with jedec registration mo-187, variation aa and ba. 11. datums -a- and -b- to be determined datum plane -h- . 12. exposed pad area in bottom side is the same as teh leadframe pad size. 5 n n-1 a b c 0.20 (n/2) tips) 2x n/2 2 1 0.60 0.50 0.60 e top view e see detail ?b? -h- 3 d -a- seating plane a 1 a 6 c 0.10 side view 0.25 bsc 4 l -c- seating plane 0.07 r. min 2 places parting line detail ?a? (scale: 30/1) 0.48 max detail ?b? (scale: 30/1) dambar protrusion 7 c 0.08 m b s a s b b 1 with plating base metal c 1 c section ?c-c? scale: 100/1 (see note 8) see detail ?a? a 2 0.05 s c c ? 3 e 1 -b- end view e1 0.95 package information vishay siliconix document number: 72817 28-jan-04 www.vishay.com 1 msop: 10-leads (power ic only) jedec part number: mo-187, (variation aa and ba) n = 10l millimeters dim min nom max note a ? ? 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.17 ? 0.27 8 b 1 0.17 0.20 0.23 8 c 0.13 ? 0.23 c 1 0.13 0.15 0.18 d 3.00 bsc 3 e 4.90 bsc e 1 2.90 3.00 3.10 3 e 0.50 bsc e 1 2.00 bsc l 0.40 0.55 0.70 4 n 10 5 0 4 6 ecn: s-40082?rev. a, 02-feb-04 dwg: 5922
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